Apple is developing AI servers built around its own M8 Ultra chips, in
two- and four-chip configurations, and evaluating Nvidia's NVLink Fusion ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌  ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ ‌ 


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TLDR

TLDR HARDWARE 2026-09-21

📱

HEADLINES AND LAUNCHES

APPLE REPORTEDLY EYES NVIDIA'S NVLINK FUSION TO CONNECT ITS OWN M8
ULTRA AI SERVERS BY 2029 (5 MINUTE READ) [4]

Apple is developing AI servers built around its own M8 Ultra chips,
in two- and four-chip configurations, and evaluating Nvidia's NVLink
Fusion, the interconnect protocol, switches, chiplets, and software
stack Nvidia uses to bind racks of GPUs into one tightly coupled
compute domain, since Apple's own UltraFusion tech stitches two chips
together but has no answer for the larger-scale connectivity these
servers would need.

CRUSOE RAISES $3.9B TO BUILD MASSIVE DATA CENTERS AND
TRUCK-TRANSPORTABLE MODULAR "SPARK" AI FACTORIES (3 MINUTE READ) [5]

Crusoe raised a $3.9 billion Series F, pushing its valuation to $30.9
billion, with the capital funding both large-scale sites like its
Abilene, Texas data center used by OpenAI, and Spark, a line of
smaller modular data centers Crusoe manufactures at its own facilities
so they can be transported by truck and connected to power almost
anywhere. Building these in-house lets Crusoe deploy compute fast
without needing a large on-site construction workforce, and the
smaller footprint helps sidestep some of the local community backlash
that larger data center complexes increasingly draw.

🔨

ENGINEERING AND APPLICATIONS

CHINA BUILDS EARLY SUB-3NM GAA TRANSISTORS USING OLDER DUV
LITHOGRAPHY, SIDESTEPPING EUV RESTRICTIONS (4 MINUTE READ) [6]

Chinese Academy of Sciences researchers have completed early
integration of stacked nanosheet-channel gate-all-around (GAA) CMOS transistors, the architecture already used by Samsung and TSMC at 3nm
and below, using deep ultraviolet (DUV) lithography instead of the EUV
machines ASML is barred from selling to China. GAA wraps the gate
fully around the channel rather than surrounding it on three sides
like FinFET, giving tighter control over current flow. Researcher Ye
Tianchun frames the work as an early process route toward sub-3nm
devices rather than a demonstrated production capability.

🧠

RESEARCH AND PROTOTYPES

NC STATE'S NEW THIN FILM IS 10,000X STIFFER THAN SILICONE, YET
INSULATES 5X BETTER (4 MINUTE READ) [7]

Material science has long treated stiffness and heat insulation as a trade-off: stiff materials like metal conduct heat fast, while soft
ones like rubber trap it. NC State researchers broke that link with a non-porous thin film built from 2D hybrid organic-inorganic
perovskites, arranging alternating organic and inorganic layers into
precise crystalline structures and swapping standard carbon chains for custom-tailored benzene rings to trap heat vibrations without
sacrificing structural rigidity.

UCLA-PIONEERED NANOWIRE NETWORKS PHYSICALLY REWIRE THEMSELVES TO
COMPUTE, NO SOFTWARE NEURAL NETWORK REQUIRED (4 MINUTE READ) [8]

A new paper in Nature Reviews Physics covers self-organizing nanowire
and nanoparticle networks, first built at UCLA in 2011, where the
material's physical structure acts as the neural network instead of
running one in software on a chip. Individual nanowires act like
neurons, and the connections between them act like synapses, growing
stronger with repeated use and fading without it, similar to memory
and forgetting in the brain, so the hardware itself learns rather than
just running a fixed program.

🎁

MISCELLANEOUS

DANIEL LEMIRE BREAKS DOWN HOW APPLE SILICON GOT 52% FASTER IN THREE
YEARS, MOSTLY FROM CLOCK SPEED (4 MINUTE READ) [9]

Comparing base M2 (2022) through M5 (2025) on Geekbench 6,
single-core performance rose 52% and multi-core 83%, with most of the single-core gain traced to raw clock speed: the P-core climbed from
3.5GHz to 4.6GHz, a 30% jump that alone explains the bulk of it.
Transistor count grew roughly 40% from M2 to M4 (20 billion to 28
billion), spent partly on two extra efficiency cores on the M4 that
boost multicore throughput without touching single-core speed, and
partly on wider decode, up from 8 to 10 instructions per cycle, ahead
of most competitors.

CEREBRAS CEO ANDREW FELDMAN ON THE "DINNER PLATE" CHIP, AND WHY AI
INFERENCE TODAY IS "UTTERLY IDIOTIC" (6 MINUTE READ) [10]

At a Google Bay View event, Cerebras co-founder Andrew Feldman,
semiconductor veteran Atiq Raza, and investor Dave Blundin discussed
where AI hardware is actually bottlenecked. Feldman brought Cerebras's
WSE-3 "dinner plate" chip, a 9-inch wafer-scale part with 4 trillion transistors across 900,000 cores, now carrying a $25 billion backlog
with plans to scale production 8x this year and again next year, and
named data center availability, not compute itself, as the industry's
current binding constraint, predicting fab capacity becomes the next
bottleneck within three years.

⚡

QUICK LINKS

NORTHROP GRUMMAN WINS GHOST-R SPY SATELLITE PROTOTYPE DEAL (3 MINUTE
READ) [11]

Northrop Grumman won a Space Force/DIU contract to build a GHOST-R
prototype satellite, using its compact suitcase-sized ESPASat-L
platform with a TRL-11 optical payload, to deliver low-cost,
high-resolution surveillance of objects in geosynchronous orbit within
an accelerated 24-month timeline.

JOBY'S AUTONOMY STACK FLIES A CONVERTED CESSNA 3,100 MILES ACROSS THE
US, NO PILOT IN CONTROL (3 MINUTE READ) [12]

Joby Aviation flew a converted Cessna Caravan more than 3,100 miles
across the US with autonomous taxiing, takeoff, navigation, and
landing throughout, remotely supervised from Joby's California
headquarters and Shaw Air Force Base, with a pilot onboard only for
compliance.

US AWARDS ANDERON $1B TO BUILD DEDICATED QUANTUM WAFER MANUFACTURING
(3 MINUTE READ) [13]

Anderon, IBM's Albany-based quantum chip foundry spinout, secured a
$1 billion CHIPS Act award to scale up US production of 300mm quantum
wafers.

LATTICE LAUNCHES MACH-N2, AN FPGA BUILT FOR THE POST-QUANTUM SECURITY
ERA (4 MINUTE READ) [14]

Lattice Semiconductor unveiled Mach-N2, an FPGA that beats rivals AMD
Xilinx and Altera to market with post-quantum cryptography (PQC) baked
in.

NEXPERIA WILL MAKE CHIPS IN INDIA WITH TATA AS IT SPLITS FROM
WINGTECH (3 MINUTE READ) [15]

Nexperia will have Tata make and package chips in India, expanding
its manufacturing options as it separates from Chinese parent
Wingtech.

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[6] https://interestingengineering.com/innovation/china-older-chipmaking-technology-smaller-chips?utm_source=tldrhardware
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